1. Field of the Invention
The invention relates generally to a method of forming a high voltage junction in a semiconductor device. More particularly, the invention relates to a method of forming a high voltage junction in a semiconductor device capable of minimizing crystal defects in a process of forming a junction structure to which a high voltage is applied and forming a junction structure of a shallow depth having a low breakdown voltage and a low sheet resistance.
2. Description of the Prior Art
A semiconductor device may be classified into a high voltage device and a low voltage device depending on its driving voltages. Of them, the high voltage device includes a high voltage transistor used in a charge pump circuit for generating a program voltage or an erase voltage of a high voltage in the flash memory device. A junction structure of the high voltage device such as the high voltage transistor (for example, source and drain of the high voltage transistor, hereinafter called ‘high voltage junction structure’) is applied with a voltage (for example, 15V) that is higher than the voltage applied to a common transistor.
This high voltage junction structure is formed by forming a high voltage DDD junction (HVN double diffused drain junction) and then performing an ion implantation process using a N+ source/drain mask. The N+ junction structure formed thus neighbors the high voltage DDD junction. Therefore, from a viewpoint that the effective length (Leff) is not reduced even though a high voltage junction breakdown of over 20V is usually required in the NAND device, it is impossible to unlimitedly increase the DDD junction.
Meanwhile, in order to maintain a satisfactory drain current, it is required that an impurity of a high concentration be implanted into a relatively narrow region. In order to form this high voltage junction, if only As is implanted as a single dopant by means of an ion implantation process, crystal defects are caused due to excess As ions. Thus, the leakage current of the junction structure is increased. In order to remove the crystal defects due to implantation of As ions, it is required that an annealing process of over 950° C. be performed. However, if the high-temperature annealing process is performed, the high voltage junction structure having a shallow depth could not be formed due to diffusion of the impurity. Further, as the activation rate of As is about 30% in the high-temperature annealing process of 950° C., there is a problem that the resistance of the high-temperature junction structure is abnormally increased.
During the high-temperature ion implantation process, if P is implanted as a single dopant instead of As, it is advantageous in lowering the sheet resistance of the high voltage junction structure and minimize generation of the defects. However, there are problems that the depth of the high voltage junction structure is increased and a shot channel effect phenomenon is generated at devices of higher-integration, due to a large diffusivity characteristic and a severe channeling phenomenon of P in the high-temperature annealing process.